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thisdocumentisageneralproductdescriptionand issubjecttochangewithoutnotice.hynixdoesnot assumeanyresponsibilityfor useofcircuitsdescribed.nopatentlicensesarei mplied. rev 1.2 / jun. 2008 1 1gbit mobile ddr sdram based on 8m x 4bank x32 i/o specification of 1gb(32mx32bit)mobileddrsdram memory cell array organizedas4banksof8,388,608x32 www..net
rev 1.2 / jun. 2008 2 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries document title 1gbit (4bank x 8m x 32bit) mobile ddr sdram revision history revision no. history draft date remark 0.1 initialdraft sep.2007 preliminary 0.2 definedidd6currentspec. dec.2007 preliminary 0.3 insertidd8spec.value(seepage23) dec.2007 p reliminary 0.4 modify:idd5:100ma>120ma idd6(@45 o c ,fullbank):450ua>500ua jan.2008 preliminary 1.0 finalversion mar.2008 1.1 modify:idd6(@45 o c ,fullbank):500ua>450ua idd6(@85 o c ,onebank):550ua>500ua may.2008 1.2 insertddr400dc/accharacteristics jun.2008 www..net
rev 1.2 / jun. 2008 3 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries features summary mobile ddr sdram doubledataratearchitecture:twodatatransfer per clockcycle mobile ddr sdram interface x32buswidth multiplexedaddress(rowaddressandcolumnad dress) supply voltage 1.8vdevice:vddandvddq=1.7vto1.95v memory cell array 1gbit(x32device)=8mx4bankx32i/o data strobe x32device:dqs0~dqs3 bidirectional,datastrobe(dqs)istransmitted andre ceivedwithdata,tobeusedincapturingdataatt he receiver dataanddatamaskreferencedtobothedgesofd qs low power features pasr(partialarrayselfrefresh) autotcsr(temperaturecompensatedselfrefresh) ds(drivestrength) dpd(deeppowerdown):dpdisanoptionalfeatur e, sopleasecontacthynixofficeforthed pdfeature input clock differentialclockinputs(ck,ck ) data mask dm0~dm3:inputmasksignalsforwritedata dmmaskswritedatainatthebothrisingand fallingedgesofthedatastrobe mode rerister set, extended mode regis- ter set and status register read keeptothejedecstandardregulation (lowpowerddrsdram) cas latency programmablecaslatency2or3supported burst length programmableburstlength2/4/8withbothse quen tialandinterleavemode auto precharge optionforeachburstaccess auto refresh and self refresh mode clock stop mode clockstopmodeisafeaturesupportedbymobile ddr sdram. keeptothejedecstandardregulation initializing the mobile ddr sdram occurringatdevicepoweruporinterruptionof device power operation temperature 30 o o ~85 o o package 90ballleadfreefbga address table note) reducedpagesize :16,384rowsby512columnsby32bits. part number page size row address column address H5MS1G22MFP 4kbyte a0~a12 a0~a9 h5ms1g32mfp 1) 2kbyte a0~a13 a0~a8 www..net
rev 1.2 / jun. 2008 4 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries description thehynixh5ms1g(2/3)2mfpseriesis1,073,741,824b itcmoslowpowerdoubledataratesynchronousdram (mobileddrsdram),ideallysuitedformobileappli cationswhichusethebatterysuchaspdas,2.5gan d3gcellular phoneswithinternetaccessandmultimediacapabili ties,mininotebook,handheldpcs.itisorganized as4banksof 8,388,608x32. thehynixh5ms1g(2/3)2mfpseriesusesadoubledata ratearchitecturetoachievehighspeedoperation. thedou bledataratearchitectureisessentiallya2 n prefetcharchitecturewithaninterfacedesignedt otransfertwodataper clockcycleatthei/opins. thehynixh5ms1g(2/3)2mfpseriesoffersfullysynch ronousoperationsreferencedtobothrisingandfal lingedgesof theclock.whilealladdressandcontrolinputsare latchedontherisingedgesoftheck(mobileddr sdramoperates fromadifferentialclock :thecrossingofckgoinghighandck goinglowisreferredtoasthepositiveedgeofc k ), data,datastrobeanddatamaskinputsaresampled onbothrisingandfallingedgesofit( inputdataisregisteredon bothedgesofdqs,andoutputdataisreferencedto bothedgesofdqs,aswellastobothedgesofck ).thedata pathsareinternallypipelinedand2bitprefetched toachievehighbandwidth.allinputvoltagelevel sarecompatible withlvcmos. readandwriteaccessestothelowpowerddrsdram (mobileddrsdram)areburstoriented;accessessta rtata selectedlocationandcontinueforaprogrammednum beroflocationsinaprogrammedsequence.accesses beginwith theregistrationofanactivecommand,whichisthe nfollowedbyareadorwritecommand.theaddress bitsreg isteredcoincidentwiththeactivecommandareused toselectthebankandtherowtobeaccessed.the addressbits registeredcoincidentwiththereadorwritecomman dareusedtoselectthebankandthestartingcolu mnlocation fortheburstaccess. thelowpowerddrsdram(mobileddrsdram)provides forprogrammablereadorwriteburstsof2,4or8 loca tions.anautoprechargefunctionmaybeenabledto provideaselftimedrowprechargethatisinitiat edattheend oftheburstaccess. aswithstandardsdram,thepipelinedandmultibank architectureoflowpowerddrsdram(mobileddrsd ram) allowsforconcurrentoperation,therebyproviding higheffectivebandwidthbyhidingrowprechargean dactivation times. thelowpowerddrsdram(mobileddrsdram)alsopro videsforspecialprogrammableselfrefreshoptions which arepartialarrayselfrefresh(full,half,quarter and1/8and1/16array)andtemperaturecompensate dselfrefresh. aburstofreadorwritecyclesinprogresscanbe interruptedandreplacedbyanewburstreadorwri tecommandon anycycle(thispipelineddesignisnotrestricted bya2nrule).onlyreadburstsinprogresswithau toprechargedisa bledcanbeterminatedbyaburstterminatecommand .burstterminatecommandisundefinedandshouldn otbe usedforreadwithautoprechargeenabledandforwr itebursts. www..net
rev 1.2 / jun. 2008 5 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries thehynixh5ms1g(2/3)2mfpserieshasthespeciallo wpowerfunctionofautotcsr(temperaturecompensa ted selfrefresh)toreduceselfrefreshcurrentconsum ption.sinceaninternaltemperaturesensorisimpl emented,itena blestoautomaticallyadjustrefreshrateaccording totemperaturewithoutexternalemrscommand. deeppowerdownmodeisanadditionaloperatingmod eforlowpowerddrsdram(mobileddrsdram).this mode canachievemaximumpowerreductionbyremovingpow ertothememoryarraywithinlowpowerddrsdram (mobileddrsdram).byusingthisfeature,thesyst emcancutoffalmostalldrampowerwithoutadding thecostof apowerswitchandgivingupmotherboardpowerlin elayoutflexibility. allinputsarelvcmoscompatible.deviceswillhave av dd andv ddq supplyof1.8v(nominal). thehynixh5ms1g(2/3)2mfpseriesisavailableinth efollowingpackage: 90 ball fbga [ size : 8mm x 13mm, t=1.0mm max ] www..net
rev 1.2 / jun. 2008 6 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries 1gb mobile ddr sdram ordering information note 1)H5MS1G22MFP:268,435,456bitbanksisorganized as8,192rowsby1,024columnsby32bits. 2)h5ms1g32mfp:268,435,456bitbanksisorganized as16,384rowsby512columnsby32bits. reducedpagesize part number clock frequency page size organization interface package H5MS1G22MFPe3m 1) 200mhz(cl3)/83mhz(cl2) 4kbyte (normal) 4banksx8mb x32 lvcmos 90ballfbga leadfree H5MS1G22MFPj3m 1) 166mhz(cl3)/83mhz(cl2) H5MS1G22MFPk3m 1) 133mhz(cl3)/83mhz(cl2) H5MS1G22MFPl3m 1) 100mhz(cl3)/66mhz(cl2) h5ms1g32mfpe3m 2) 200mhz(cl3)/83mhz(cl2) 2kbyte (reduced) h5ms1g32mfpj3m 2) 166mhz(cl3)/83mhz(cl2) h5ms1g32mfpk3m 2) 133mhz(cl3)/83mhz(cl2) h5ms1g32mfpl3m 2) 100mhz(cl3)/66mhz(cl2) www..net
rev 1.2 / jun. 2008 7 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries information for hynix known good die withtheadventofmultichippackage(mcp),packag eonpackage(pop)andsysteminapackage(sip)ap plications, customerdemandforknowngooddie(kgd)hasincrea sed. requirementsforsmallerformfactorsandhigherme morydensitiesarefuelingtheneedforwaferlevel memorysolu tionsduetotheirsuperiorflexibility.hynixknow ngooddie(kgd)productscanbeusedinpackaging technologies suchassystemsinapackage(sip)andmultichipp ackage(mcp)toreducetheboardarearequired,mak ingthem idealforhandheldpcs,andmanyotherportabledi gitalapplications. hynixmobilesdramwillbeabletocontinueitscon stanteffortofenablingtheadvancedpackageprodu ctsofallappli cationcustomers. pleasecontacthynixofficeforhynixkgdproduct availabilityandinformations. www..net
rev 1.2 / jun. 2008 8 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries 90ball fbga assignment vss vddq vssq vddq vssq vdd cke a9 dq31 dq29 dq27 dq25 dqs3 dm3 ck a11 b c d e f g h a6 a7 j a4 dm1 k vssq dq30 dq28 dq26 dq24 nc /ck a8 a5 vddq dq17 dq19 dq21 dq23 a13 /we /cs a10 a2 dq16 dq18 dq20 dq22 dqs2 dm2 /cas ba0 a0 dm0 vdd vssq vddq vssq vddq vss /ras ba1 a1 a3 1 2 3 4 5 6 7 8 9 vssq vddq vssq dqs1 dq9 dq11 l m n vddq dq13 p vss dq15 r dq8 dq10 dq12 dq14 vssq dq7 dq5 dq3 dq1 vddq dqs0 dq6 dq4 dq2 dq0 vddq vssq vddq vssq vdd a a12 top view www..net
rev 1.2 / jun. 2008 9 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries mobile ddr sdram pin descriptions symbol type description ck,ck input clock:ckandck aredifferentialclockinputs.alladdressandcon trolinputsignalsare sampledonthecrossingofthepositiveedgeofck andnegativeedgeofck .output(read) dataisreferencedtothecrossingsofckandck (bothdirectionsofcrossing). cke input clockenable:ckehighactivates,andckelowdeact ivatesinternalclocksignals,device inputbuffersandoutputdrivers.takingckelowpr ovidesprechargepowerdown andselfrefreshoperation(allbanksidle),oract ivepowerdown(rowactivein anybank).ckeissynchronousforallfunctionsexc eptforselfrefreshexit,whichis achievedasynchronously. cs input chipselect:cs enables(registeredlow)anddisables(registered high)thecommand decoder.allcommandsaremaskedwhencs isregisteredhigh.cs providesforexternal bankselectiononsystemswithmultiplebanks.cs isconsideredpartofthecommand code. ras ,cas ,we input commandinputs:ras ,cas andwe (alongwithcs )definethecommandbeingentered ba0,ba1 input bankaddressinputs:ba0andba1definetowhichba nkanactive,read,writeor prechargecommandisbeingapplied.ba0andba1als odeterminewhichmoderegister istobeloadedduringamoderegistersetcommand (mrs,emrsorsrr). a0~a13 input addressinputs:providetherowaddressforactive commands,andthecolumnaddress andautoprechargebitforread/writecommands,to selectonelocationoutofthe memoryarrayintherespectivebank.theaddressin putsalsoprovidetheopcodeduring amoderegistersetcommand.a10sampledduringap rechargecommanddeter mineswhethertheprechargeappliestoonebank(a1 0low)orallbanks(a10high). ifonlyonebankistobeprecharged,thebankiss electedbyba0,ba1. for1gb(x32),rowaddress:a0~a12andcolumnadd ress:a0~a9with4kbytepage size.rowaddresa0~a13columaddress:a0~a8w ith2kbytepagesize. autoprechargeflag:a10 dq0~dq31 i/o databus:datainput/outputpin dm0~dm3 input inputdatamask:dmisaninputmasksignalforwri tedata.inputdataismaskedwhen dmissampled.highalongwiththatinputdataduri ngawriteaccess.dmissampled onbothedgesofdqs.datamaskpinsincludedummy loadinginternally,tomatchthedq anddqsloading. forx32devices,dm0correspondstothedataondq0 dq7,dm1correspondstothedata ondq8dq15,dm2correspondstothedataondq16dq 23,anddm3correspondstothe dataondq24dq31. dqs0~dqs3 i/o datastrobe:outputwithreaddata,inputwithwrit edata.edgealignedwithreaddata, centeralignedwithwritedata.usedtocapturewri tedata.forx32device,dqs0corre spondstothedataondq0dq7,dqs1correspondsto thedataondq8dq15,dqs2cor respondstothedataondq16dq23,anddqs3corresp ondstothedataondq24dq31. v dd supply powersupply v ss supply ground v ddq supply i/opowersupply v ssq supply i/oground nc noconnect:nointernalelectricalconnectionis present. www..net
rev 1.2 / jun. 2008 10 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries functional block diagram 8mbit x 4banks x 32 i/o mobile ddr sdram 32 senseamp&i/ogate outputbuffer&logic address register moderegister statemachine addressbuffers bankselect rowactive cas latency clk cke /cs /ras /cas /we dm0 ~dm3 a0 a1 ba1 ba0 a13 pasr refresh dq0 dq31 rowdecoders rowdecoders rowdecoders rowdecoders columndecoders 8mx32bank0 8mx32bank1 8mx32bank2 8mx32bank3 memory cell array dataoutcontrol burst length /clk inputbuffer&logic ds 64 32 64 datastrobe transmitter datastrobe receiver ds dqs0 ~ dqs3 extended mode register selfrefresh logic&timer internalrow counter writedataregister 2bitprefetchunit row pre decoder column pre decoder columnadd counter burst counter columnactive www..net
rev 1.2 / jun. 2008 11 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries register definition i mode register set (mrs) for mobile ddr sdram ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 0 0 0 caslatency bt burstlength burst type a3 burst type 0 sequential 1 interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 0 0 0 reserved reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved www..net
rev 1.2 / jun. 2008 12 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries register definition ii extended mode register set (emrs) for mobile ddr sd ram ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 0 0 0 0 0 0 0 0 ds 0 0 pasr ds (drivestrength) a6 a5 drive strength 0 0 full 0 1 half(default) 1 0 quarter 1 1 octant pasr (partialarrayselfrefresh) a2 a1 a0 self refresh coverage 0 0 0 allbanks(default) 0 0 1 halfoftotalbank(ba1=0) 0 1 0 quarteroftotalbank(ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved 1 0 1 oneeighthoftotalbank (ba1=ba0=rowaddressmsb=0) 1 1 0 onesixteenthoftotalbank (ba1=ba0=rowaddress2msbs=0) 1 1 1 reserved www..net
rev 1.2 / jun. 2008 13 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries register definition iii status register (sr) for mobile ddr sdram note) 1.therevisionnumberstartsat0000andincreme ntsby0001eachtimeachangeinthemanufacture rsspecification,ibis,or processoccurs. 2.lowtemperatureoutofrange. 3.hightemperatureoutofrangenorefreshrate canguaranteefunctionality. 4.therefreshratemultiplierisbasedonthememo rystemperaturesensor. 5.requiredaverageperiodicrefreshinterval=tre fi*multiplier. 6.statusregisterisonlyforread. 7.toreadoutstatusregistervalues,ba[1:0]set to01banda[13:0]settoall0withmrscommandfo llowedbyreadcommand withthatba[1:0]anda[13:0]aredontcare.ifth epagesizeis4kbyte,a[12:0]areprovided. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 density dw refreshrate revisionidentification manufa cturersidentification 0 1 1 0 1 x x x x 1) x 1) x 1) x 1) 0 1 1 0 density dq15 dq14 dq13 density 0 0 0 128 0 0 1 256 0 1 0 512 0 1 1 1024 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved dw (devicewidth) dq11 device width 0 16bits 1 32bits refresh rate dq10 dq9 dq8 refresh rate 0 0 x 4 2) 0 1 0 4 0 1 1 2 1 0 0 1 1 0 1 0.5 1 1 0 0.25 1 1 1 0.25 3) manufacturers identification dq3 dq2 dq1 dq0 manufacturer 0 1 1 0 hynix x x x x reservedor othercompanies www..net
rev 1.2 / jun. 2008 14 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries command truth table dm truth table note: 1.allstatesandsequencesnotshownareillegalo rreserved. 2.deslectandnoparefunctionallyinterchangeable . 3.autoprechargeisnonpersistent.a10highenable sautoprecharge,whilea10lowdisablesautoprechar ge 4.burstterminateappliestoonlyreadburstswith autoprechargedisabled.thiscommandisundefined andshouldnotbeusedfor readwithautoprechargeenabled,andforwriteburs ts. 5.thiscommandisburstterminateifckeishigha nddeeppowerdownentryifckeislow. 6.ifa10islow,bankaddressdetermineswhichban kistobeprecharged.ifa10ishigh,allbanksar eprechargedandba0ba1are don ' tcare. 7.thiscommandisautorefreshifckeishigh,and selfrefreshifckeislow. 8.alladdressinputsandi/oare '' don ' tcare '' exceptforcke.internalrefreshcounterscontrol bankandrowaddressing. 9.allbanksmustbeprechargedbeforeissuingana utorefreshorselfrefreshcommand. 10.ba0andba1valueselectamongmrs,emrsandsr r. 11.usedtomaskwritedata,providedcoincidentwi ththecorrespondingdata. 12.ckeishighforallcommandsshownexceptself refreshanddeeppowerdown. function cs ras cas we ba a10/ap addr note deselect(nop) h x x x x x x 2 nooperation(nop) l h h h x x x 2 active(selectbankandactivaterow) l l h h v row row read(selectbankandcolumnandstartreadburst) l h l h v l col readwithap(readburstwithautoprecharge) l h l h v h c ol 3 write(selectbankandcolumnandstartwrite burst) l h l l v l col writewithap(writeburstwithautoprecharge) l h l l v h col 3 burstterminateorenterdeeppowerdown l h h l x x x 4,5 precharge(deactivaterowinselectedbank) l l h l v l x 6 prechargeall(deactivaterowsinallbanks) l l h l x h x 6 autorefreshorenterselfrefresh l l l h x x x 7,8,9 moderegisterset l l l l v opcode 10 function dm dq note writeenable l valid 11 writeinhibit h x 11 www..net
rev 1.2 / jun. 2008 15 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries cke truth table note: 1.ckenisthelogicstateofckeatclockedge n ;cke n 1wasthestateofckeatthepreviousclockedge. 2.currentstateisthestateoflpddrimmediately priortoclockedge n . 3.command n isthecommandregisteredatclockedgen,andact ion n istheresultofcommand n . 4.allstatesandsequencesnotshownareillegalo rreserved. 5.deselectandnoparefunctionallyinterchangeabl e. 6.powerdownexittime(t xp )shouldelapsebeforeacommandotherthannopor deselectisissued. 7.selfrefreshexittime(t xsr )shouldelapsebeforeacommandotherthannopor deselectisissued. 8.thedeeppowerdownexitproceduremustbefollo wedasdiscussedinthedeeppowerdownsectionof thefunctionaldescription. 9.theclockmusttoggleatleastonetimeduringt het xp period. 10.theclockmusttoggleatleastonceduringthe t xsr time. cke n-1 cke n current state command n action n note l l powerdown x maintainpowerdown l l selfrefresh x maintainselfrefresh l l deeppowerdown x maintaindeeppower down l h powerdown nopordeselect exitpowerdown 5,6,9 l h selfrefresh nopordeselect exitselfrefresh 5,7,1 0 l h deeppowerdown nopordeselect exitdeeppowerdow n 5,8 h l allbanksidle nopordeselect prechargepower downentry 5 h l bank(s)active nopordeselect activepowerdown entry 5 h l allbanksidle autorefresh selfrefreshentry h l allbanksidle burstterminate enterdeeppower down h h seetheothertruthtables www..net
rev 1.2 / jun. 2008 16 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries current state bank n truth table (commandtobank n ) note: 1.thetableapplieswhenbothcke n 1andcke n arehigh,andaftert xsr ort xp hasbeenmetifthepreviousstatewasselfrefres h orpowerdown. 2.deselectandnoparefunctionallyinterchangeabl e. 3.allstatesandsequencesnotshownareillegalo rreserved. 4.thiscommandmayormaynotbebankspecific.if allbanksarebeingprecharged,theymustbeina validstateforprecharging. 5.acommandotherthannopshouldnotbeissuedto thesamebankwhileareadorwriteburstwithaut oprechargeisenabled. 6.thenewreadorwritecommandcouldbeautoprec hargeenabledorautoprechargedisabled. current state command action notes cs ras cas we description any h x x x deselect(nop) continuepreviousoperation l h h h nop continuepreviousoperation idle l l h h active selectandactivaterow l l l h autorefresh autorefresh 10 l l l l moderegisterset moderegisterset 10 l l h h precharge noactionifbankisidle rowactive l h l h read selectcolumn&startreadburst l h l l write selectcolumn&startwriteburst l l h l precharge deactivaterowinbank(orbanks) 4 read (withoutauto recharge) l h l h read truncateread& startnewreadburst 5,6 l h l l write truncateread& startnewwriteburst 5,6,13 l l h l precharge truncateread,startprecharge l h h l burstterminate burstterminate 11 write (withoutauto precharge) l h l h read truncatewrite& startnewreadburst 5,6,12 l h l l write truncatewrite& startnewwriteburst 5,6 l l h l precharge truncatewrite,startprecharge 12 www..net
rev 1.2 / jun. 2008 17 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries 7.currentstatedefinitions: idle:thebankhasbeenprecharged,andtrphas beenmet. rowactive:arowinthebankhasbeenactivated ,andt rcd hasbeenmet. nodatabursts/accessesandnoregisteraccesses areinprogress. read:areadbursthasbeeninitiated,withauto prechargedisabled,andhasnotyetterminatedor beenterminated. write:awritebursthasbeeninitiated,withau toprechargedisabled,andhasnotyetterminatedo rbeenterminated. 8.thefollowingstatesmustnotbeinterruptedby acommandissuedtothesamebank. deselectornopcommandsorallowablecommands totheotherbankshouldbeissuedonanyclockedg eoccurring duringthesestates.allowablecommandstothe otherbankaredeterminedbyitscurrentstateand truthtable3, andaccordingtotruthtable4. precharging:startswiththeregistrationofa prechargecommandandendswhent rp ismet. oncet rp ismet,thebankwillbeintheidlestate. rowactivating:startswithregistrationofan activecommandandendswhent rcd ismet. oncet rcd ismet,thebankwillbeinthe '' rowactive '' state. readwithapenabled:startswiththeregistrat ionofthereadcommandwithautoprechargeenabled andends whent rp hasbeenmet.oncet rp hasbeenmet,thebankwillbeintheidlestate. writewithapenabled:startswithregistration ofawritecommandwithautoprechargeenabledand ends whent rp hasbeenmet.oncet rp ismet,thebankwillbeintheidlestate. 9.thefollowingstatesmustnotbeinterruptedby anyexecutablecommand;deselectornopcommandsmu stbeapplied toeachpositiveclockedgeduringthesestates . refreshing:startswithregistrationofanauto refreshcommandandendswhent rfc ismet. oncet rfc ismet,thelpddrwillbeinan '' allbanksidle '' state. accessingmoderegister:startswithregistrati onofamoderegistersetcommandandendswhentmr dhasbeenmet. oncet mrd ismet,thelpddrwillbeinan '' allbanksidle '' state. prechargingall:startswiththeregistrationo faprechargeallcommandandendswhent rp ismet. oncet rp ismet,thebankwillbeintheidlestate. 10.notbankspecific;requiresthatallbanksare idleandnoburstsareinprogress. 11.notbankspecific.burstterminateaffectsthe mostrecentreadburst,regardlessofbank. 12.requiresappropriatedmmasking. 13.awritecommandmaybeappliedafterthecomple tionofthereadburst;otherwise,aburstterminat emustbeusedtoend thereadpriortoassertingawritecommand. www..net
rev 1.2 / jun. 2008 18 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries current state bank n truth table (commandtobank m ) current state command action notes cs ras cas we description any h x x x deselect(nop) continuepreviousoperation l h h h nop continuepreviousoperation idle x x x x any anycommandallowedtobankm rowactivating, active,orpre charging l l h h active activaterow l h l h read startreadburst 8 l h l l write startwriteburst 8 l l h l precharge precharge readwithauto prechargedis abled l l h h active activaterow l h l h read startreadburst 8 l h l l write startwriteburst 8,10 l l h l precharge precharge writewithauto prechargedis abled l l h h active activaterow l h l h read startreadburst 8,9 l h l l write startwriteburst 8 l l h l precharge precharge readwithauto precharge l l h h active activaterow l h l h read startreadburst 5,8 l h l l write startwriteburst 5,8,10 l l h l precharge precharge writewithauto precharge l l h h active activaterow l h l h read startreadburst 5,8 l h l l write startwriteburst 5,8 l l h l precharge precharge www..net
rev 1.2 / jun. 2008 19 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries note: 1.thetableapplieswhenbothcke n 1andcke n arehigh,andaftert xsr ort xp hasbeenmetifthepreviousstatewas selfrefreshorpowerdown. 2.deselectandnoparefunctionallyinterchangeabl e. 3.allstatesandsequencesnotshownareillegalo rreserved. 4.currentstatedefinitions: idle:thebankhasbeenprecharged,and trphasbeenmet. rowactive:arowinthebankhasbeen activated,andt rcd hasbeenmet.nodatabursts/accessesand noregisteraccessesareinprogress. read:areadbursthasbeeninitiated, withautoprechargedisabled,andhasnotyettermi natedorbeenterminated. write:awritebursthasbeeninitiated ,withautoprechargedisabled,andhasnotyetter minatedorbeenterminated. 5.readwithapenabledandwritewithapenabled: thereadwithautoprechargeenabledorwritewitha utoprecharge enabledstatescanbebrokenintotwop arts:theaccessperiodandtheprechargeperiod.f orreadwithap,the prechargeperiodisdefinedasifthes ameburstwasexecutedwithautoprechargedisabled andthenfollowedwiththe earliestpossibleprechargecommandtha tstillaccessesallthedataintheburst.forwri tewithautoprecharge,the prechargeperiodbeginswhent wr ends,witht wr measuredasifautoprechargewasdisabled.theac cessperiodstarts withregistrationofthecommandanden dswheretheprechargeperiod(ort rp )begins.duringtheprechargeperiod, ofthereadwithautoprechargeenabled orwritewithautoprechargeenabledstates,active, precharge,read,and writecommandstotheotherbankmaybe applied;duringtheaccessperiod,onlyactiveand prechargecommands totheotherbanksmaybeapplied.ine ithercase,allotherrelatedlimitationsapply(e. g.contentionbetweenreaddata andwritedatamustbeavoided). 6.autorefresh,selfrefresh,andmoderegisterse tcommandsmayonlybeissuedwhenallbankareidl e. 7.aburstterminatecommandcannotbeissuedtoan otherbank; itappliestothebankrepresentedbyt hecurrentstateonly. 8.readsorwriteslistedinthecommandcolumninc ludereadsandwriteswithautoprechargeenableda nd readsandwriteswithautoprechargedi sabled. 9.requiresappropriatedmmasking. 10.awritecommandmaybeappliedafterthecomple tionofdataoutput,otherwiseaburstterminateco mmand mustbeissuedtoendthereadpriorto assertingawritecommand. www..net
rev 1.2 / jun. 2008 20 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries absolute maximum rating ac and dc operating conditions operating condition clock inputs (ck,ck ) address and command inputs (a0~an,ba0,ba1,cke,cs ,ras ,cas ,we ) data inputs (dq,dm,dqs) data outputs (dq,dqs) parameter symbol rating unit operatingcasetemperature t c 30~85 o o storagetemperature t stg 55~150 o o voltageonanypinrelativetov ss v in ,v out 0.3~v ddq +0.3 v voltageonv dd relativetov ss v dd 0.3~2.7 v voltageonv ddq relativetov ss v ddq 0.3~2.7 v shortcircuitoutputcurrent i os 50 ma powerdissipation p d 0.7 w parameter symbol min typ max unit note supplyvoltage v dd 1.7 1.8 1.95 v 1 i/osupplyvoltage v ddq 1.7 1.8 1.95 v 1 operatingcasetemperature t c 30 85 o o parameter symbol min max unit note dcinputvoltage v in 0.3 v ddq+ 0.3 v dcinputdifferentialvoltage v id(dc) 0.4*v ddq v ddq+ 0.6 v 2 acinputdifferentialvoltage v id(ac) 0.6*v ddq v ddq+ 0.6 v 2 acdifferentialcrosspointvoltage v ix 0.4*v ddq 0.6*v ddq v 3 parameter symbol min max unit note inputhighvoltage v ih 0.8*v ddq v ddq+ 0.3 v inputlowvoltage v il 0.3 0.2*v ddq v parameter symbol min max unit note dcinputhighvoltage v ihd(dc) 0.7*v ddq v ddq+ 0.3 v dcinputlowvoltage v ild(dc) 0.3 0.3*v ddq v acinputhighvoltage v ihd(ac) 0.8*v ddq v ddq+ 0.3 v acinputlowvoltage v ild(ac) 0.3 0.2*v ddq v parameter symbol min max unit note dcoutputhighvoltage(ioh=0.1ma) v oh 0.9*v ddq v dcoutputlowvoltage(iol=0.1ma) v ol 0.1*v ddq v www..net
rev 1.2 / jun. 2008 21 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries leakage current note: 1.allvoltagesarereferencedtovss=0vandvssq mustbesamepotentialandvddqmustnotexceedth elevelofvdd. 2.vid(dc)andvid(ac)arethemagnitudeofthedif ferencebetweentheinputlevelonckandtheinput levelonck . 3.thevalueofvixisexpectedtobe0.5*vddqand musttrackvariationsinthedclevelofthesame. 4.v in =0to1.8v.allotherpinsarenottestedunderv in =0v. 5.d out isdisabled.v out =0to1.95v. ac operating test condition note:1.thecircuitshownontherightrepresents thetiming loadusedindefiningtherelevanttimingparameter sof thepart.itisnotintendedtobeeitheraprecise repre sentationofthetypicalsystemenvironmentnorad epic tionoftheactualloadpresentedbyaproductiont ester. systemdesignerswilluseibisorothersimulation tools tocorrelatethetimingreferenceloadtosystemen viron ment.manufacturerswillcorrelatetotheirproduct ion (generallyacoaxialtransmissionlineterminateda tthe testerelectronics).forthehalfstrengthdriverw itha nominal10pfloadparameterstacandtqhare expectedtobeinthesamerange.however,these parametersarenotsubjecttoproductiontestbuta re estimatedbydesignandcharacterization.useofib isorothersimulationtoolsforsystemdesignvali dationissuggested. input / output capacitance note: 1.thesevaluesareguaranteedbydesignandarete stedonasamplebaseonly. 2.thesecapacitancevaluesareforsinglemonolith icdevicesonly.multiplediepackageswillhavepa rallelcapacitiveloads. 3.inputcapacitanceismeasuredaccordingtojep14 7procedureformeasuringcapacitanceusingavecto rnetworkanalyzer.vdd, vddqareappliedandallotherpins(exceptthepin undertest)floating.dq ' sshouldbeinhighimpedancestate.thismaybe achievedbypullingcketolowlevel. 4.althoughdmisaninputonlypin,theinputcapa citanceofthispinmustmodeltheinputcapacitanc eofthedqanddqspins.this isrequiredtomatchsignalpropagationtimesofdq ,dqsanddminthesystem. parameter symbol min max unit note inputleakagecurrent i li 1 1 ua 4 outputleakagecurrent i lo 1.5 1.5 ua 5 parameter symbol value unit note acinputhigh/lowlevelvoltage v ih /v il 0.8*v ddq /0.2*v ddq v inputtimingmeasurementreferencelevelvoltage v trip 0.5*v ddq v inputrise/falltime t r /t f 1 ns outputtimingmeasurementreferencelevelvoltage v outref 0.5*v ddq v outputloadcapacitanceforaccesstimemeasurement cl pf 1 parameter symbol speed unit note min max inputcapacitance,ck,ck cck 1.5 3.5 pf inputcapacitancedelta,ck,ck cdck 0.25 pf inputcapacitance,allotherinputonlypins ci 1.5 3 .0 pf inputcapacitancedelta,allotherinputonlypins cdi 0.5 pf input/outputcapacitance,dq,dm,dqs cio 2.0 4.5 pf 4 input/outputcapacitancedelta,dq,dm,dqs cdio 0. 5 pf 4 testloadforfulldrivestrengthbuffer (20pf) testloadforhalfdrivestrengthbuffer (10pf) output z o =50 www..net
rev 1.2 / jun. 2008 22 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries mobile ddr output slew rate characterristics note: 1.measuredwithatestloadof20pfconnectedtov ssq 2.outputslewrateforrisingedgeismeasuredbet weenvild(dc)tovihd(ac)andforfallingedgebetw eenvihd(dc)tovild(ac) 3.theratioofpullupslewratetopulldownslew rateisspecifiedforthesametemperatureandvol tage,overtheentiretemperature andvoltagerange.foragivenoutput,itrepresent sthemaximumdifferencebetweenpullupandpulld owndriversduetoprocess variation. mobile ddr ac overshoot / undershoot specification note: 1.thisspecificationisintendedfordeviceswith noclampprotectionandisguaranteedbydesign. parameter min max unit note pullupandpulldownslewrateforfullstrengthd river 0.7 2.5 v/ns 1,2 pullupandpulldownslewrateforhalfstrengthd river 0.3 1.0 v/ns 1,2 outputslewratematchingratio(pulluptopulldo wn) 0.7 1.4 3 parameter specification maximumpeakamplitudeallowedforovershoot 0.5v maximumpeakamplitudeallowedforundershoot 0.5v theareabetweenovershootsignalandvddmustbel essthanorequalto 3vns theareabetweenundershootsignalandgndmustbe lessthanorequalto 3vns 2.5v 2.0v 1.5v 1.0v 0.5v 0.0v 0.5v overshoot undershoot vdd vss max.amplitude=0.5v max.area=3vns time(ns) voltage(v) www..net
rev 1.2 / jun. 2008 23 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries dc characteristics parameter symbol test condition max unit note ddr 400 ddr 333 ddr 266 ddr 200 operatingonebank activeprecharge current 4 kbytes pagesize idd0 trc=trc(min);tck=tck(min);ckeishigh; cs ishighbetweenvalidcommands;addressin putsareswitching;databusinputsarestable 90 70 60 50 ma 1,6 2kbytes pagesize 80 60 50 50 prechargepowerdown standbycurrent idd2p allbanksidle;ckeislow;cs ishigh; tck=tck(min);addressandcontrolinputsare switching;databusinputsarestable 0.4 ma prechargepowerdown standbycurrent withclockstop idd2ps allbanksidle;ckeislow;cs ishigh; ck=low;ck =high;addressandcontrolin putsareswitching;databusinputsarestable 0.4 ma prechargenonpowerdown standbycurrent idd2n allbanksidle;ckeishigh;cs ishigh, tck=tck(min);addressandcontrolinputsare switching;databusinputsarestable 15 12 ma prechargenonpowerdown standbycurrent withclockstop idd2ns allbanksidle;ckeishigh;cs ishigh; ck=low;ck =high;addressandcontrolin putsareswitching;databusinputsarestable 8 6 activepowerdown standbycurrent idd3p onebankactive;ckeislow;cs ishigh; tck=tck(min);addressandcontrolinputsare switching;databusinputsarestable 3 ma activepowerdown standbycurrent withclockstop idd3ps onebankactive;ckeislow;cs ishigh; ck=low;ck =high;addressandcontrolin putsareswitching;databusinputsarestable 2 activenonpowerdown standbycurrent idd3n onebankactive;ckeishigh;cs ishigh; tck=tck(min); addressandcontrolinputsare switching;databusinputsarestable 15 12 ma activenonpowerdown standbycurrent withclockstop idd3ns onebankactive;ckeishigh;cs ishigh; ck=low;ck =high;addressandcontrolin putsareswitching;databusinputsarestable 8 6 ma operatingburstreadcurrent idd4r onebankactive;bl=4;cl=3;tck=tck(min); continuousreadbursts;i out =0ma;addressin putsareswitching,50%datachangeeach bursttransfer 150 130 110 90 ma 1 operatingburstwritecurrent idd4w onebankactive;bl=4;tck=tck(min);continu ouswritebursts;addressinputsareswitching; 50%datachangeeachbursttransfer 140 120 100 80 ma autorefreshcurrent idd5 trc=trfc(min);tck=tck(min);burstrefresh; ckeishigh;addressandcontrolinputsare switching;databusinputsarestable 120 ma selfrefreshcurrent idd6 ckeislow;ck=low;ck =high; extendedmoderegistersettoall0's;address andcontrolinputsarestable;databusinputs arestable seenextpage ua 2 deeppowerdowncurrent idd8 address,controlanddat abusinputsarestable 10 ua 4 www..net
rev 1.2 / jun. 2008 24 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries note: 1.iddspecificationsaretestedafterthedevicei sproperlyinitialized 2.inputslewrateis1v/ns 3.definitionsforidd: lowisdefinedasv in 0.1*v ddq highisdefinedasv in 0.9*v ddq stableisdefinedasinputsstableatahighor lowlevel switchingisdefinedas addressandcommand:inputschangi ngbetweenhighandlowoncepertwoclockcycles databusinputs:dqchangingbetwe enhighandlowonceperclockcycle dmanddqs arestable 4.pleasecontacthynixofficeformoreinformation andabilityfordpdoperation.deeppowerdownope rationisahynixoptional function. 5.alliddvaluesareguaranteedbyfullrangeofo peratingvoltageandtemperature. vdd,vddq=1.7v~1.95v.temperature=30 o c~+85 o c 6.H5MS1G22MFPseries:4kbytepagesize,h5ms1g32 mfpseries:2kbytepagesize dc characteristics - i dd6 note: 1.relatednumericalvaluesinthis45 o careexamplesforreferencesamplevalueonly. 2.withaonchiptemperaturesensor,autotemperat urecompensatedselfrefreshwillautomaticallyadj usttheintervalofselfrefresh operationaccordingtocasetemperaturevariations. temp. ( o c) memory array unit 4 banks 2 banks 1 bank 45 450 350 300 ua 85 900 650 500 ua www..net
rev 1.2 / jun. 2008 25 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries ac characteristics (acoperatingconditionsunlessotherwisenoted)(s heet1of2) parameter symbol ddr400 ddr333 ddr266 ddr200 unit note min max min max min max min max dqoutputaccesstime(fromck,ck ) t ac 2.0 5.0 2.0 5.0 2.5 6.0 2.5 7.0 ns dqsoutputaccesstime(fromck,ck ) t dqsck 2.0 5.0 2.0 5.0 2.5 6.0 2.5 7.0 ns clockhighlevelwidth t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clocklowlevelwidth t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clockhalfperiod t hp tcl, tch (min) tcl, tch (min) tcl, tch (min) tcl, tch (min) ns 1,2 systemclockcycletime cl=3 t ck3 5 6.0 7.5 10 ns 3 cl=2 t ck2 12 12 12 15 ns dqanddminputsetuptime t ds 0.54 0.6 0.8 1.1 ns 4,5,6 dqanddminputholdtime t dh 0.54 0.6 0.8 1.1 ns 4,5,6 dqanddminputpulsewidth t dipw 1.6 1.6 1.6 2.2 ns 7 addressandcontrolinputsetuptime t is 0.9 1.1 1.3 1.5 ns 6,8,9 addressandcontrolinputholdtime t ih 0.9 1.1 1.3 1.5 ns 6,8,9 addressandcontrolinputpulsewidth t ipw 2.2 2.2 2.6 3.0 ns 7 dq&dqslowimpedancetimefromck,ck t lz 1.0 1.0 1.0 1.0 ns 10 dq&dqshighimpedancetimefromck,ck t hz 5.0 5.0 6.0 7.0 ns 10 dqsdqskew t dqsq 0.4 0.5 0.6 0.7 ns 11 dq/dqsoutputholdtimefromdqs t qh thp tqhs thp tqhs thp tqhs thp tqhs ns 2 dataholdskewfactor t qhs 0.5 0.65 0.75 1.0 ns 2 writecommandto1stdqslatchingtransi tion t dqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqsinputhighlevelwidth t dqsh 0.4 0.4 0.4 0.4 tck dqsinputlowlevelwidth t dqsl 0.4 0.4 0.4 0.4 tck dqsfallingedgeofcksetuptime t dss 0.2 0.2 0.2 0.2 tck dqsfallingedgeholdtimefromck t dsh 0.2 0.2 0.2 0.2 tck www..net
rev 1.2 / jun. 2008 26 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries ac characteristics (acoperatingconditionsunlessotherwisenoted)(s heet2of2) parameter symbol ddr400 ddr333 ddr266 ddr200 unit note min max min max min max min max moderegistersetcommandperiod t mrd 2 2 2 2 tck mrs(srr)toreadcommandperiod t srr 2 2 2 2 tck minimum time between status register readtonextvalidcommand t src cl+1 cl+1 cl+1 cl+1 tck writepreamblesetuptime t wpres 0 0 0 0 ns 12 writepostamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 13 writepreamble t wpre 0.25 0.25 0.25 0.25 tck readpreamble cl=3 t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck 14 cl=2 t rpre 0.5 1.1 0.5 1.1 0.5 1.1 0.5 1.1 tck 14 readpostamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck activetoprechargecommandperiod t ras 40 70,00 0 42 70,00 0 45 70,00 0 50 70,00 0 ns activetoactivecommandperiod t rc 55 60 75 80 ns autorefreshtoactive/autorefresh commandperiod t rfc 110 110 110 110 ns activetoreadorwritedelay t rcd 15 18 22.5 30 ns 15 prechargecommandperiod t rp 15 18 22.5 30 ns 15 activebank a toactivebank b delay t rrd 10 12 15 15 ns writerecoverytime t wr 15 15 15 15 ns autoprechargewriterecovery+precharge time t dal (twr/tck)+(trp/tck) tck 16 internalwritetoreadcommanddelay t wtr 2 1 1 1 tck selfrefreshexittonextvalidcommandde lay t xsr 140 140 140 140 ns exitpowerdowntonextvalidcommandde lay t xp tis+ 2clk tis+ 1clk tis+ 1clk tis+ 1clk ns cke min .pulsewidth(highandlow) t cke 1 1 1 1 tck averageperiodicrefreshinterval t refi 7.8 7.8 7.8 7.8 us 17 refreshperiod t ref 64 64 64 64 ms www..net
rev 1.2 / jun. 2008 27 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries note: 1.min(t cl ,t ch )referstothesmalleroftheactualclocklowtim eandtheactualclockhightimeasprovidedtothe device (i.e.thisvaluecanbegreaterthantheminimum specificationlimitsfort cl andt ch ) 2.t qh =t hp t qhs ,wherethp=minimumhalfclockperiodforanygiv encycleandisdefinedbyclockhighorclocklow (t cl ,t ch ). t qhs accountsfor1)thepulsedurationdistortionofo nchipclockcircuits;and2)theworstcasepusho utofdqsononetransition followedbytheworstcasepullinofdqonthenex ttransition,bothofwhichare,separately,dueto datapinskewandoutput patterneffects,andpchanneltonchannelvariati onoftheoutputdrivers. 3.theonlytimethattheclockfrequencyisallowe dtochangeisduringclockstop,powerdownorsel frefreshmodes. 4.thetransitiontimefordq,dmanddqsinputsis measuredbetweenv il (dc)tov ih (ac)forrisinginputsignals,andv ih (dc)to v il (ac)forfallinginputsignals. 5.dqs,dmanddqinputslewrateisspecifiedtop reventdoubleclockingofdataandpreservesetupa ndholdtimes.signaltransitions throughthedcregionmustbemonotonic. 6.inputslewrate 1.0v/ns. 7.theseparametersguaranteedevicetimingbutthe yarenotnecessarilytestedoneachdevice. 8.thetransitiontimeforaddressandcommandinpu tsismeasuredbetweenv ih andv il . 9.ack/ck differentialslewrateof2.0v/nsisassumedfor thisparameter. 10.t hz andt lz transitionsoccurinthesameaccesstimewindows asvaliddatatransitions.theseparametersarenot referredtoa specificvoltagelevel,butspecifywhenthedevice isnolongerdriving(hz),orbeginsdriving(lz). 11.t dqsq consistsofdatapinskewandoutputpatterneffec ts,andpchanneltonchannelvariationoftheout putdriversforany givencycle. 12.thespecificrequirementisthatdqsbevalid( high,low,orsomepointonavalidtransition)on orbeforethisckedge.avalid transitionisdefinedasmonotonicandmeetingthe inputslewratespecificationsofthedevice.when nowriteswerepreviouslyin progressonthebus,dqswillbetransitioningfrom hiztologiclow.ifapreviouswritewasinprog ress,dqscouldbehigh, low,ortransitioningfromhightolowatthistime ,dependingont dqss . 13.themaximumlimitforthisparameterisnotad evicelimit.thedeviceoperateswithagreaterval ueforthisparameter,butsystem performance(busturnaround)willdegradeaccording ly. 14.alowlevelondqsmaybemaintainedduringhig hzstates(dqsdriversdisabled)byaddingaweak pulldownelementinthe system.itisrecommendedtoturnofftheweakpull downelementduringreadandwritebursts(dqsdri versenabled). 15.speedbin(clt rcd t rp )=333 16.minimum3clkoftdal(=twr+trp)isrequiredbec auseitneedminimum2clkfortwrandminimum1clk fortrp. t dal =(t wr /t ck )+(t rp /t ck ):foreachofthetermsabove,ifnotalreadyani nteger,roundtothenexthigherinteger. 17.amaximumofeightrefreshcommandscanbepost edtoanygivenlowpowerddrsdram(mobileddrsdr am),meaningthat themaximumabsoluteintervalbetweenanyrefreshc ommandandthenextrefreshcommandis8*t refi . 18.allacparametersareguaranteedbyfullrange ofoperatingvoltageandtemperature. vdd,vddq=1.7v~1.95v.temperature=30 o o o o www..net
rev 1.2 / jun. 2008 28 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries mobile ddr sdram operation statediagram idle allbank pcg. auto refresh self refresh pcg. power down (e)mrs set write read precharge all active power down row active mrs, emrs refs ckel refa ckeh act ckel ckeh write write read refsx commandinput automatic sequence deep power down power on pcg. all banks power applied dpds dpdsx burst stop writea read reada bst reada writea writea reada read pre pre pre srr read srr read reada act: active b st: b urst ckel: e nterpow erdow n ckeh : e xitpow erdow n dpds: e nterdeep pow erdow n dpdsx: e xitdeeppow er dow nem r s e m rs: e xt.m odereg. set m r s: m oderegisterset pr e: precharge pr eall: prechargeall b anks r efa: autor efresh r efs: e nterselfr efresh r efsx: e xitselfrefresh r ead: r eadw /oauto precharge r eada: r eadw ithauto precharge w r ite: w ritew /oauto precharge w r itea: w ritew ithauto precharge sr r: statusr egister r ead www..net
rev 1.2 / jun. 2008 29 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries deselect thedeselectfunction(cs =high)preventsnewcommandsfrombeingexecuted bythemobileddrsdram.the mobileddrsdramiseffectivelydeselected.operati onsalreadyinprogressarenotaffected. nooperation thenooperation(nop)commandisusedtoperforma noptoamobileddrsdramthatisselected(cs =low). thispreventsunwantedcommandsfrombeingregister edduringidleorwaitstates.operationsalreadyi nprogressare notaffected.(seetonextfigure) active theactivecommandisusedtoactivatearowinap articularbankforasubsequentreadorwriteacces s.thevalueof theba0,ba1inputsselectsthebank,andtheaddres sprovidedona0a13(only2kbytepagesize.ifthe 4kbytespage size,a0~a12areprovided)selectstherow.(seeto nextfigure) beforeanyreadorwritecommandscanbeissuedto abankwithinthemobileddrsdram,arowinthatb ank mustbeopened.thisisaccomplishedviatheactive command,whichselectsboththebankandtherowt obeacti vated. therowremainsactiveuntilaprecharge(orreadw ithautoprechargeorwritewithautoprecharge)co m mandisissuedtothebank. aprecharge(orreadwithautoprechargeorwritew ithautoprecharge)commandmustbeissuedbefore openingadifferentrowinthesamebank. cs a0~a13 we cas don't care clk clk cke ba0,ba1 bank address row address don't care ra ba nopcommand activecommand ras cs a0~a13 w e cas clk clk cke ba0, ba1 ras (high) (high) www..net
rev 1.2 / jun. 2008 30 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries oncearowisopen(withanactivecommand)aread orwritecommandmaybeissuedtothatrow,subject tothe t rcd specification.t rcd ( min )shouldbedividedbytheclockperiodandrounded uptothenextwholenumberto determinetheearliestclockedgeaftertheactive commandonwhichareadorwritecommandcanbeent ered. asubsequentactivecommandtoadifferentrowint hesamebankcanonlybeissuedaftertheprevious activerow hasbeenclosed(precharge).theminimumtimeinter valbetweensuccessiveactivecommandstothesame bankis definedbyt rc . asubsequentactivecommandtoanotherbankcanbe issuedwhilethefirstbankisbeingaccessed,whic hresultsin areductionoftotalrowaccessoverhead.theminim umtimeintervalbetweensuccessiveactivecommands todiffer entbanksisdefinedbyt rrd. d on't c are oncearow isopen(w ithanactivecom m and)areado rw ritecom m andm aybeissuedtothatrow ,subject tothe trcdspecification.trcd(m in)shouldbedividedby theclockperiodandroundeduptothenextw hole num berto determ inetheearliestclockedgeaftertheactive com m andonwhichareadorw ritecom m andcanbeent ered . /clk clk n op nop nop nop trcd com m and address w ritea w itha/p bankb act nop banka act banka col bankb row banka row banka act banka row trrd trc www..net
rev 1.2 / jun. 2008 31 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries read/writecommand thereadcommandisusedtoinitiateaburstreadt oanactiverow.thevalueofba0andba1selectst hebankand addressinputsselectthestartingcolumnlocation. thevalueofa10determineswhetherornotautopre chargeisused.ifautoprechargeisselected,the rowbeing accessedwillbeprechargedattheendoftheread burst;ifautoprechargeisnotselected,theroww illremainopen forsubsequentaccess.thevaliddataoutelements willbeavailablecaslatencyafterthereadcomman disissued. themobileddrdrivesthedqsduringreadoperation s.theinitiallowstateofthedqsisknownasthe readpreamble andthelastdataoutelementiscoincidentwithth ereadpostamble.dqsisedgealignedwithreaddat a.uponcom pletionofaburst,assumingnonewreadcommandsh avebeeninitiated,thei/o'swillgohighz. thewritecommandisusedtoinitiateaburstwrite accesstoanactiverow.thevalueofba0,ba1sel ectsthebank andaddressinputsselectthestartingcolumnlocat ion. thevalueofa10determineswhetherornotautopre chargeisused.ifautoprechargeisselected,ther owbeing accessedwillbeprechargedattheendofthewrite burst;ifautoprechargeisnotselected,therow willremainopen forsubsequentaccess.inputdataappearingonthe databus,iswrittentothememoryarraysubjectto thedminput logiclevelappearingcoincidentwiththedata.if agivendmsignalisregisteredlow,thecorrespond ingdatawillbe writtentothememory;ifthedmsignalisregister edhigh,thecorrespondingdatainputswillbeigno red,andawrite willnotbeexecutedtothatbyte/columnlocation. thememorycontrollerdrivesthedqsduringwriteo perations.the initiallowstateofthedqsisknownasthewrite preambleandthelowstatefollowingthelastdata inelementiswrite postamble.uponcompletionofaburst,assumingno newcommandshavebeeninitiated,thei/o'swillst ayhighz andanyadditionalinputdatawillbeignored. whenreadorwritecommandissues,thea0~a8(colum naddress)areprovidedifonly2kbytespagesizea sshown belowfigure.ifthepagesizeis4kbytes,thea0~a 9(columnaddress)areprovided. read/writecommand don't care ca ba high to enable auto precharge low to disable auto precharge read com m and w rite com m and ca ba clk clk cke clk clk cke (high) (high) cs a0~a8 w e cas a10 ras ba0, ba1 cs a0~a8 w e cas a10 ras ba0, ba1 www..net
rev 1.2 / jun. 2008 32 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries read thebasicreadtimingparametersfordqareshownn extfigure(basicreadtimingparameters).theyapp lytoall readoperations.duringreadbursts,dqsisdriven bythemobileddrsdramalongwiththeoutputdata. theinitial lowstateofthedqsisknownasthereadpreamble; thelowstatecoincidentwithlastdataoutelemen tisknownas thereadpostamble. basicreadtimingparameters d o n d o n+ 1 d o n+ 2 d o n+ 3 /c lk clk tck tck tc h tc l tr pre td q sc k td q sq m ax ta c tlz tq h td q sc k tq h tq h th z tq h tr pr e td q sc k tlz td q sc k trpst ta c td q s q m ax d o n d o n+ 1 d o n+ 2 d o n + 3 d q s d q d q s d q d o n 't c a re 1)d o n :d a tao utfrom co lu m n n 2)alld q arevaildta c afterth ec kedge alld q arevaildtd q sq afterth ed q sedge,rega rdlessofta c trpst ta c m a x ta c m in tq h th z www..net
rev 1.2 / jun. 2008 33 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries thefirstdataoutelementisedgealignedwiththe firstrisingedgeofdqsandthesuccessivedatao utelementsare edgealignedtosuccessiveedgesofdqs.thisissh owninnextfigurewithacaslatencyof2and3. uponcompletionofareadburst,assumingnoother readcommandhasbeeninitiated,thedqwillgoto highz. r eadburstshowingcaslatency /clk clk do n do n read nop nop nop nop nop ba, col n cl=3 cl=2 don'tcare 1)do n :dataoutfromcolumnn 2)ba,col n =banka,columnn 3)burstlength=4;3subseqnentelementsofdata outappearintheprogrammedorderfollowingdo n 4)shownwithnominaltac,tdqsckandtdqsq command address dqs dq dqs dq www..net
rev 1.2 / jun. 2008 34 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries readtoread datafromareadburstmaybeconcatenatedortrunc atedbyasubsequentreadcommand.thefirstdataf romthe newburstfollowseitherthelastelementofacomp letedburstorthelastdesiredelementofalonger burstthatis beingtruncated.thenewreadcommandshouldbeiss uedxcyclesafterthefirstreadcommand,wherex equals thenumberofdesireddataoutelementpairs(pairs arerequiredbythe2nprefetcharchitecture). consecutivereadbursts areadcommandcanbeinitiatedonanyclockcycle followingapreviousreadcommand.nonconsecutive readsare showninthefirstfigureofnextpage.randomread accesseswithinapageorpagescanbeperformeda sshownin secondfigureofnextpage. /c lk c lk d o n d o n rea d n o p r ea d n o p n o p n o p ba , c ol n c l= 3 c l= 2 d on'tc are 1)d o n (or b ):d ataoutfrom colum nn(orcolum nb) 2)ba ,c ol n(b) = banka ,c olum nn(b) 3)burstlength= 4or8(if4 ,theburstsareconc atenated;if8,thesecondburstinterruptsthefir st) 4)r eadburstsaretoanactiverow inany bank 5)show nw ithnom inalta c,td q sc kandtd q sq co m m an d a ddress d q s d q d q s d q ba , c ol b d o b d o b www..net
rev 1.2 / jun. 2008 35 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries nonconsecutivereadbursts randomreadbursts / c l k c l k d o n d o n r e a d n o p n o p r e a d n o p n o p b a , c o l n c l = 3 c l = 2 d o n 't c a r e 1 ) d o n ( o r b ) : d a t a o u t fr o m c o lu m n n ( o r c o lu m n b ) 2 ) b a , c o l n ( b ) = b a n k a ,c o lu m n n ( b ) 3 ) b u r s t l e n g t h = 4 ; 3 s u b s e q u e n t e le m e n t s o f d a t a o u t a p p e a r in th e p r o g r a m m e d o r d e r fo llo w in g d o n ( b ) 4 ) s h o w n w it h n o m in a lt a c ,t d q s c k a n d t d q s q c o m m a n d a d d r e s s d q s d q d q s d q b a , c o l b d o b / c l k c l k d o n d o x ' d o n r e a d r e a d r e a d r e a d n o p n o p b a , c o l n c l = 3 c l = 2 d o n 't c a r e 1 ) d o n , e t c : d a t a o u t f r o m c o lu m n n , e t c n ', x ', e t c : d a t a o u t e le m e n t s , a c c o d in g t o t h e p r o g r a m m d b u r s t o r d e r 2 ) b a , c o l n = b a n k a , c o lu m n n 3 ) b u r s t l e n g t h = 2 , 4 o r 8 in c a s e s s h o w n ( i f b u r s t o f 4 o r 8 , t h e b u r s t is in t e r r u p t e d ) 4 ) r e a d a r e t o a c t i v e r o w s in a n y b a n k s c o m m a n d a d d r e s s d q s d q d q s d q b a , c o l b d o b b a , c o l x b a , c o l g d o n ' d o x d o x ' d o b ' d o g d o g ' d o n ' d o x d o b d o b ' www..net
rev 1.2 / jun. 2008 36 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries readburstterminate datafromanyreadburstmaybetruncatedwithabu rstterminatecommand.theburstterminatelatency is equaltotheread(cas)latency,i.e.,theburstte rminatecommandshouldbeissuedxcyclesafterthe readcom mandwherexequalsthedesireddataoutelementpa irs. terminatingareadburst /clk clk r ead burst term inate n o p n o p n o p n o p ba, col n cl= 3 cl= 2 d on'tcare 1)d o n :d ataoutfrom colum nn 2)ba,col n = banka,colum nn 3)casesshow nareburstsof4or8term inatedafte r2dataelem ents 4)show nw ithnom inaltac,td q sckandtd q sq com m and address d q s dq d q s dq www..net
rev 1.2 / jun. 2008 37 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries readtowrite datafromreadburstmustbecompletedortruncated beforeasubsequentwritecommandcanbeissued.i ftrun cationisnecessary,theburstterminatecommandmu stbeused,asshowninnextfig.forthecaseofn ominal t dqss . readtowrite /clk clk d o n d o n read bst n o p w r ite n o p ba, col n cl= 3 cl= 2 don'tcare 1)d o n = d atao utfrom colum nn;d ib= d ataintocolum n b 2)burstlength= 4or8inthecasesshow n;ifthe burstlengthis2,thebstcom m andcanbeom m itted 3)show nw ithnom inaltac,td q sckandtd qsq com m and address d q s d q d q s d q ba, col b n o p dm read bst n o p n o p n o p ba, col n com m and address ba, col b w rite td qss d i b di b www..net
rev 1.2 / jun. 2008 38 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries readtoprecharge areadburstmaybefollowedbyortruncatedwitha prechargecommandtothesamebank(providedauto pre chargewasnotactivated).theprechargecommandsh ouldbeissuedxcyclesafterthereadcommand,whe rex equalthenumberofdesireddataoutelementpairs. followingtheprechargecommand,asubsequentcomma ndtothesamebankcannotbeissueduntiltrpism et. notethatpartoftherowprechargetimeishidden duringtheaccessofthelastdataoutelements.in thecaseofa readbeingexecutedtocompletion,aprechargecomm andissuedattheoptimumtime(asdescribedabove) pro videsthesameoperationthatwouldresultfromrea dburstwithautoprechargeenabled. thedisadvantageoftheprechargecommandisthati trequiresthatthecommandandaddressbusesbeav ailableat theappropriatetimetoissuethecommand.theadva ntageoftheprechargecommandisthatitcanbeus edto truncatebursts. readtoprecharge /clk clk do n do n read nop pre nop nop act ba, col n cl=3 cl=2 don'tcare 1)do n =dataoutfromcolumnn 2)casesshownareeitheruninterruptedburstof4, orinterruptedburstsof8 3)shownwithnominaltac,tdqsckandtdqsq 4)prechargemaybeappliedat(bl/2)tckaftert hereadcommand. 5)notethatprechargemaynotbeissuedbeforetra snsaftertheactivecommandforapplicablebanks. 6)theactivecommandmaybeappliediftrchasbee nmet. command address dqs dq dqs dq bank ( aorall) ba, row trp www..net
rev 1.2 / jun. 2008 39 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries write inputdataappearingonthedatabus,iswrittento thememoryarraysubjecttothedminputlogiclev elappearing coincidentwiththedata.ifagivendmsignalisr egisteredlow,thecorrespondingdatawillbewritt entothememory; ifthedmsignalisregisteredhigh,thecorrespond ingdatainputswillbeignored,andawritewilln otbeexecutedto thatbyte/columnlocation. basicwritetimingparametersfordqareshowninf igure;theyapplytoallwriteoperations. basicwritetimingparameters duringwritebursts,thefirstvaliddatainelemen twillberegisteredonthefirstrisingedgeofdq sfollowingthe writecommand,andthesubsequentdataelementswil lberegisteredonsuccessiveedgesofdqs.thelow stateof dqsbetweenthewritecommandandthefirstrising edgeiscalledthewritepreamble,andthelowstat eondqs followingthelastdatainelementiscalledthewr itepostamble. thetimebetweenthewritecommandandthefirstco rrespondingrisingedgeofdqs(t dqss )isspecifiedwitharel ativelywiderangefrom75 % to125 % ofaclockcycle.nextfig.showsthetwoextremes oft dqss foraburstof4. uponcompletionofaburst,assumingnoothercomma ndshavebeeninitiated,thedqwillremainhighz andany additionalinputdatawillbeignored. /c lk c lk tc k tc h tc l d in d in d q s d q s d q ,d m d q ,d m td q ss td q sh td sh td sh tw pst tw pr es td s td h tw pre td s td h tw pr es tw pre td q ss td q sh tw pst td ss td ss td q sl d o n 't c a re 1)d in:d atainforcolum nn 2)3subseq uentelem entsofd atainareap p lied in thep rog ram m ed ord erfollow ing d in 3)td q ss:eachrising edg eofd q sm ustfallw ithin the+ /25(p ercentage)w ind ow ofthecorresp onding positiveclockedg e td q sl case1: td q ss= m in case2: td q ss= m ax www..net
rev 1.2 / jun. 2008 40 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries writeburst(min.andmax.t dqss ) /clk clk w rite nop no p no p nop ba, col b td qss min don'tcare 1)dib=dataintocolum nb 2)3subsequentelem entsofdatainareappliedin theprogram m edorderfollowingdib 3)anoninterruptedburstof4isshown 4)a10islowwiththew ritecom m and(autoprecharg eisdisabled) command address dqs dq dqs dq no p d m d m tdqss m ax www..net
rev 1.2 / jun. 2008 41 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries writetowrite dataforanywriteburstmaybeconcatenatedwitho rtruncatedwithasubsequentwritecommand.ineit hercase, acontinuousflowofinputdata,canbemaintained. thenewwritecommandcanbeissuedonanypositiv eedgeof theclockfollowingthepreviouswritecommand.the firstdatainelementfromthenewburstisapplied aftereither thelastelementofacompletedburstorthelastd esireddataelementofalongerburstwhichisbein gtruncated.the newwritecommandshouldbeissuedxcyclesaftert hefirstwritecommand,wherexequalsthenumbero f desireddatainelementpairs. concatenatedwritebursts /clk clk write nop write nop nop ba, col b tdqss min don'tcare 1)di b ( n )=dataintocolumnb(columnn) 2)3subsequentelementsofdatainareappliedin theprogrammedorderfollowingdib. 3subsequentelementsofdatainareappliedin theprogrammedorderfollowingdin. 3)noninterruptedburstsof4areshown. 4)eachwritecommandmaybetoanyactivebank command address dqs dq dqs dq nop dm dm ba, col n di b di n di b di n tdqss max www..net
rev 1.2 / jun. 2008 42 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries nonconcatenatedwritebursts randomwritecycles /c lk c l k w r it e n o p n o p w r it e n o p b a , c o l b d on 'tc a re 1 )d i b ( n )= d a ta in to co lu m n b (o rco lu m n n ). 2 )3 su b se q u e n te le m e n tso fd a ta in a re a p p lie d in th e p ro g ra m m e d o rd e rfo llo w in g d i b . 3 su b se q u e n te le m e n tso fd a ta in a re a p p lie d in th e p ro g ra m m e d o rd e rfo llo w in g d i n . 3 )n o n in te rru p te d b u rstso f4 a re sh o w n . 4 )e a ch w r it e co m m a n d m a yb e to a n y a ctive b a n k a n d m a yb e to th e sa m e o rd iffe re n td e v ice s . c om m a n d a d d ress d q s d q n o p d i b d m td q s s m a x d i n b a , c o ln /c lk c lk w r it e w r it e w r it e w r it e n o p b a , c ol b d on'tc are 1 )d ibetc.= d a tainto colum nb,e tc. ;b',etc.= th enextd ata info llo w in gd ib,etc. a cco rdingto theprogram m edburstorder 2 )pro gram m edburstlength = 2,4or8incasessho w n.ifburstof4 or8,burstw ouldbetruncate d. 3 )eachw r it eco m m andm aybe toan yactiveban kan d m aybeto thesam e o rdiffe rentdevices. c om m and a d d ress w r it e b a , c ol n b a , c ol x ba , c ol a b a , c ol g d q s d m td q ss m ax d q d i b d i b ' d i x d i x' d i n d i n ' d i a d i a' www..net
rev 1.2 / jun. 2008 43 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries writetoread dataforanywriteburstmaybefollowedbyasubse quentreadcommand.tofollowawritewithouttrunc atingthe writeburst,twtrshouldbemetasshowninfigure. dataforanywriteburstmaybetruncatedbyasubs equentreadcommandasshowninfigure.notethatt heonly datainpairsthatareregisteredpriortothet wtr periodarewrittentotheinternalarray,andany subsequentdatain mustbemaskedwithdm. /clk clk write nop nop nop nop ba, col b don'tcare 1)di b =dataintocolumnb.3subsequentelementsofd atainareappliedintheprogrammedorderfollowing dib. 2)anoninterruptedburstof4isshown. 3)twtrisreferencedfromthepositiveclockedgea fterthelastdatainpair. 4)a10islowwiththewritecommand(autoprecharge isdisabled) 5)thereadandwritecommandsaretothesamedevi cebutnotnecessarilytothesamebank. command address dqs dq read dm tdqss max ba, col n twtr cl=3 nop di b www..net
rev 1.2 / jun. 2008 44 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries interruptingwritetoread /clk clk write nop nop read nop ba, col b don'tcare 1)di b =dataintocolumnb.do n =dataoutfromcolumnn. 2)aninterruptedburstof4isshown,2dataeleme ntsarewritten. 3subsequentelementsofdatainareappliedin theprogrammedorderfollowingdib. 3)twtrisreferencedfromthepositiveclockedge afterthelastdatainpair. 4)a10islowwiththewritecommand(autoprecharg eisdisabled) 5)thereadandwritecommandsaretothesamedevi cebutnotnecessarilytothesamebank. command address dqs dq nop dm tdqss max twtr cl=3 nop di b ba, col n do n www..net
rev 1.2 / jun. 2008 45 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries writetoprecharge dataforanywriteburstmaybefollowedbyasubse quentprechargecommandtothesamebank(provided auto prechargewasnotactivated).tofollowawritewit houttruncatingthewriteburst,twrshouldbemet asshownin fig. noninterruptingwritetoprecharge /clk clk write nop nop nop pre ba, col b don'tcare 1)dib(n)=dataintocolumnb(columnn) 3subsequentelementsofdatainareappliedin theprogrammedorderfollowingdib. 2)anoninterruptedburstsof4areshown. 3)twrisreferencedfromthepositiveclockedgea fterthelastdatainpair. 4)a10islowwiththewritecommand(autoprecharg eisdisabled) command address dqs dq nop dm tdqss max ba (aorall) twr di b www..net
rev 1.2 / jun. 2008 46 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries dataforanywriteburstmaybetruncatedbyasubs equentprechargecommandasshowninfigure. notethatonlydatainpairsthatareregisteredpr iortothet wr periodarewrittentotheinternalarray,andany subse quentdatainshouldbemaskedwithdm,asshownin nextfig.followingtheprechargecommand,asubse quent commandtothesamebankcannotbeissueduntiltrp ismet. interruptingwritetoprecharge /clk clk write nop nop nop nop ba, col b don'tcare 1)dib=dataintocolumnb. 2)aninterruptedburstof4or8isshown,2data elementsarewritten. 3)twrisreferencedfromthepositiveclockedgea fterthelastdesireddatainpair. 4)a10islowwiththewritecommand(autoprecharg eisdisabled) 5)*1=canbedon'tcareforprogrammedburstleng thof4 6)*2=forprogrammedburstlengthof4,dqsbecom esdon'tcareatthispoint command address dqs dq pre dm tdqss max twr di b * 2 * 1 * 1 * 1 * 1 ba (aorall) www..net
rev 1.2 / jun. 2008 47 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries burstterminate theburstterminatecommandisusedtotruncaterea dbursts(withautoprechargedisabled).themostr ecently registeredreadcommandpriortotheburstterminat ecommandwillbetruncated,asshownintheoperat ionsec tionofthisdatasheet.notetheburstterminateco mmandisnotbankspecific.thiscommandshouldnot beused toterminatewritebursts. thebelowfigureshowsincaseof2kbytepagesize. ifthepagesizeis4kbyte,a0~a12areprovided. burstterminatecommand don't care cs a0~a13 we cas clk clk cke ba0,ba1 ras (high) www..net
rev 1.2 / jun. 2008 48 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries precharge theprechargecommandisusedtodeactivatetheope nrowinaparticularbankortheopenrowinallb anks. anothercommandtothesamebank(orbanks)beingp rechargedmustnotbeissueduntiltheprechargeti me(t rp )is completed. ifonebankistobeprecharged,theparticularban kaddressneedstobespecified.ifallbanksaret obeprecharged, a10shouldbesethighalongwiththeprechargecom mand.ifa10ishigh,ba0andba1areignored.apr echarge commandwillbetreatedasanopifthereisnoope nrowinthatbank,orifthepreviouslyopenrowi salreadyinthe processofprecharging. thebelowfigureshowsincaseof2kbytepagesize. ifthepagesizeis4kbyte,a0~a9,a11anda12are provided. prechargecommand autoprecharge autoprechargeisafeaturewhichperformsthesame individualbankprechargefunctionasdescribedab ove,butwith outrequiringanexplicitcommand. thisisaccomplishedbyusinga10(a10=high),toen ableautoprechargeinconjunctionwithaspecific readorwrite command.thisprechargesthebank/rowaftertherea dorwriteburstiscomplete. autoprechargeisnonpersistent,soitshouldbee nabledwithareadorwritecommandeachtimeauto prechargeis desired.autoprechargeensuresthataprechargeis initiatedattheearliestvalidstagewithinabur st. theusermustnotissueanothercommandtothesame bankuntiltheprechargetime(t rp )iscompleted. don't care ba bank address a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is precharged. if a10 = high when read or write command, auto- precharge function is enabled. while a10 = low, auto- precharge function is disabled. cs a0~a9, a11~a13 we cas clk clk cke ba0, ba1 ras a10 (high) www..net
rev 1.2 / jun. 2008 49 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries autorefreshandselfrefresh mobileddrdevicesrequirearefreshofallrowsin anyrolling64msinterval.eachrefreshisgenerat edinoneoftwo ways:byanexplicitautorefreshcommand,orbyan internallytimedeventinselfrefreshmode: - autorefresh. thiscommandisusedduringnormaloperationofthe mobileddr.itisnonpersistent,somustbeissue deachtimea refreshisrequired.therefreshaddressingisgene ratedbytheinternalrefreshcontroller.themobile ddrrequires autorefreshcommandsatanaverageperiodicinterv aloft refi . toallowforimprovedefficiencyinschedulingand switchingbetweentasks,someflexibilityintheab soluterefresh intervalisprovided.amaximumofeightautorefre shcommandscanbepostedtoanygivenmobileddr, andthe maximumabsoluteintervalbetweenanyautorefresh commandandthenextautorefreshcommandis8*t refi . selfrefresh. thisstateretainsdatainthemobileddr,evenif therestofthesystemispowereddown(evenwithou texternalclock ing).noterefreshintervaltimingwhileinselfre freshmodeisscheduledinternallyinthemobiledd randmayvary andmaynotmeettrefitime. ''don'tcare''exceptcke,whichmustremainlow.a ninternalrefreshcycleisscheduledonselfrefre shentry.thepro cedureforexitingselfrefreshmoderequiresaser iesofcommands.firstclockmustbestablebefore ckegoinghigh. nopcommandsshouldbeissuedforthedurationoft herefreshexittime(t xsr ),becausetimeisrequiredforthecom pletionofanyinternalrefreshinprogress. theuseofselfrefreshmodeintroducesthepossibi litythataninternallytimedeventcanbemissedw henckeis raisedforexitfromselfrefreshmode.uponexitf romselfrefreshanextraautorefreshcommandisr ecom mended.intheselfrefreshmode,twoadditionalpo wersavingoptionsexist.theyaretemperaturecomp ensatedself refreshandpartialarrayselfrefreshandaredesc ribedintheextendedmoderegistersection. theselfrefreshcommandisusedtoretaincelldat ainthemobilesdram.intheselfrefreshmode,th emobilesdram operatesrefreshcycleasynchronously. theselfrefreshcommandisinitiatedlikeanauto refreshcommandexceptckeisdisabled(low).them obileddr canaccomplishanspecialselfrefreshoperationby thespecificmodes(pasr)programmedinextendedm oderegis ters.themobileddrcancontroltherefreshratea utomaticallybythetemperaturevalueofautotcsr (temperature compensatedselfrefresh)toreduceselfrefreshcu rrentandselectthememoryarraytoberefreshedb ythevalueof pasr(partialarrayselfrefresh).themobileddrc anreducetheselfrefreshcurrent(i dd6 )byusingthesetwo modes. thefigureofnextpageshowsincaseof2kbytepag esize.ifthepagesizeis4kbyte,a0~a12areprov ided. www..net
rev 1.2 / jun. 2008 50 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries don'tcare autorefreshcommand selfrefreshcommand cs a0~a13 we cas clk clk cke ba0, ba1 ras cs a0~a13 we cas clk clk cke ba0, ba1 ras (high) www..net
rev 1.2 / jun. 2008 51 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries selfrefreshentryandexit /clk clk enter self refresh mode pre nop arf nop nop nop arf nop act pre all cke command address a10(ap) dq baa row n row n high-z exit self refresh mode any command (auto refresh recommended) cont't care trp trfc txsr trfc www..net
rev 1.2 / jun. 2008 52 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries moderegisterset themoderegisterandtheextendedmoderegisterar eloadedviatheaddressbits.ba0andba1areused toselect amongthemoderegister,theextendedmoderegister andstatusregister.seethemoderegisterdescrip tioninthe registerdefinitionsection.themoderegisterset commandcanonlybeissuedwhenallbanksareidle andno burstsareinprogress,andasubsequentexecutable commandcannotbeissueduntilt mrd ismet. thebelowfigureshowsincaseof2kbytepagesize. ifthepagesizeis4kbyte,a0~a12areprovided. mode register set command code=moderegister/extendedmoderegisterselec tion (ba0,ba1)andopcode(a0an) tmrd definition mrs nop valid code valid tmrd /clk clk command address don't care d o n 't c a re c ode c ode c s a 0 ~ a 13 w e c a s c l k c l k c k e b a 0 ,b a 1 r a s (h igh ) www..net
rev 1.2 / jun. 2008 53 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries mode register themoderegistercontainsthespecificmodeofope rationofthemobileddrsdram.thisregisterinclu destheselec tionofaburstlength(2,4or8),acaslatency(2 or3),abursttype.themoderegistersetmustbe donebeforeany activatecommandafterthepowerupsequence.anyc ontentsofthemoderegisterbealteredbyreprogr ammingthe moderegisterthroughtheexecutionofmoderegiste rsetcommand. mode register set burst length readandwriteaccessestothemobileddrsdramare burstoriented,withtheburstlengthbeingprogra mmable,as showninpage10.theburstlengthdeterminesthema ximumnumberofcolumnlocationsthatcanbeaccess edfora givenreadorwritecommand.burstlengthsof2,4 or8locationsareavailableforboththesequentia landthe interleavedbursttypes. burst type accesseswithinagivenburstmaybeprogrammedto beeithersequentialorinterleaved. cas latency thecaslatencyisthedelaybetweentheregistrati onofareadcommandandtheavailabilityofthefi rstpieceofout putdata.ifareadcommandisregisteredatacloc kedge n andthelatencyis3clocks,thefirstdataelemen twillbe validat n +2t ck +t ac .ifareadcommandisregisteredataclockedge n andthelatencyis2clocks,thefirstdata elementwillbevalidat n +t ck +t ac . clk clk precharge allbank mode register set cm d tck comm and (any) 0 1 2 3 4 5 6 trp 2 clk m in www..net
rev 1.2 / jun. 2008 54 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries extended mode register theextendedmoderegistercontainsthespecificfe aturesofselfrefreshoperationofthemobileddr sdram. theextendedmoderegisterisprogrammedviathemo deregistersetcommand(withba1=1andba0=0)and willretainthestoredinformationuntilitisrepr ogrammed,thedeviceisputindeeppowerdownmode ,orthedevice losespower.theextendedmoderegistershouldbel oadedwhenallbanksareidleandnoburstsarein progress,and subsequentoperationshouldonlybeinitiatedafter t mrd .violatingtheserequirementswillresultinunspe cifiedopera tion. theextendedmoderegisteriswrittenbyasserting lowoncs ,ras ,cas ,we andhighonba0.thestateofaddress pinsa0~a13(ora12whichdependsonpagesize)a ndba1inthesamecycleascs ,ras ,cas andwe goingloware writtenintheextendedmoderegister.theextended moderegistermustbeloadedwhenallbanksareid leandno burstsareinprogress,andthecontrollermustwai tthespecifiedtimebeforeinitiatinganysubseque ntoperation.vio latingeitheroftheserequirementswillresultin unspecifiedoperation. thisregisterincludestheselectionofpartialarr aytoberefreshed(fullarray,halfarray,quarter array,etc.).the extendedmoderegistersetmustbedonebeforeany activatecommandafterthepowerupsequence.anyc ontentsof themoderegisterbealteredbyreprogrammingthe moderegisterthroughtheexecutionofextendedmod eregister setcommand. partial array self refresh (pasr) withpasr,theselfrefreshmayberestrictedtoa variableportionofthetotalarray.thewholearra y(default),1/2 array,1/4array,1/8arrayor1/16arraycouldbe selected. drive strength (ds) thedrivestrengthcouldbesettofullorhalfvia addressbitsa5anda6.thehalfdrivestrengthis intendedforlighter loadsorpointtopointenvironments. www..net
rev 1.2 / jun. 2008 55 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries statusregisterread thestatusregistercontainsthespecificdieinfor mationsuchasdensity,devicetype,databuswidth ,refreshrate, revisionidandmanufacturers.thestatusregister isonlyforread.belowfigureisstatusregisterr eadtimingdia gram. toreadoutthestatusregistervalues,ba[1:0]set to01banda[13:0]settoall0withmrscommandf ollowedby readcommandwiththatba[1:0]anda[13:0]aredon tcare.ifthepagesizeis4kbyte,a[12:0]arepro vided. note) 1.srrcanonlybeissuedafterpowerupsequencei scomplete. 2.srrcanonlybeissuedwithallbanksprecharged . 3.srrclisunchangedfromvalueinthemoderegis ter. 4.srrblisfixedat2. 5.tsrr=2clk(min) 6.tsrc=cl+1.(mintimebetweenreadtonextva lidcommand) 7.nocommandsotherthannopanddeselectareallo wedbetweenthesrrandtheread. cmd tck trp tsrr nop mrs nop read nop nop nop cmd register value out tsrc clk clk cmd ba[1:0] add dqs dq[15:0] 01 0 cl = 3 don t care pre all or pre www..net
rev 1.2 / jun. 2008 56 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries powerdown powerdownoccursifckeissetlowcoincidentwith devicedeselectornopcommandandwhennoaccesse sarein progress.ifpowerdownoccurswhenallbanksarei dle,itisprechargepowerdown. ifpowerdownoccurswhenoneormorebanksareact ive,itisreferredtoasactivepowerdown.thede vicecannot stayinthismodeforlongerthantherefreshrequi rementsofthedevice,withoutlosingdata.thepow erdownstateis exitedbysettingckehighwhileissuingadeviced eselectornopcommand. avalidcommandcanbeissuedaftert xp .forclockstopduringpowerdownmode,pleaseref ertotheclockstopsub sectioninoperationsectionofthisdatasheet. note:thiscaseshowsckelowcoincidentwithnoop eration. alternatelypowerdownentrycanbeachie vedwithckelowcoincidentwithdevicedeselect. deeppowerdown thedeeppowerdown(dpd)modeenablesverylowsta ndbycurrents.allinternalvoltagegeneratorsinsi dethe mobileddrsdramarestoppedandallmemorydatais lostinthismode. alltheinformationinthemoderegisterandtheex tendedmoderegisterislost.nextfigure, deeppowerdown command showsthedeeppowerdowncommandallbanksmustb einidlestatewithnoactivityonthedatabus priortoenteringthedpdmode.whileinthisstate ,ckemustbeheldinaconstantlowstate. toexitthedpdmode,ckeistakenhighafterthec lockisstableandnopcommandmustbemaintainedf oratleast 200us.after200usacompletereinitializationr outingisrequiredfollowingsteps4through11as definedinpower upandinitializationsequences.dpdisanoptional feature,sopleasecontacthynixofficefordpdfe ature. thebelowfigureshowsincaseof2kbytepagesize. ifthepagesizeis4kbyte,a0~a12areprovided. don't care don't care deeppowerdownentrycommand powerdownentrycommand cs a0~a13 we cas clk clk cke ba0, ba1 ras cs a0~a13 we cas clk clk cke ba0, ba1 ras www..net
rev 1.2 / jun. 2008 57 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries mobileddrsdramdeeppowerdownentryandexit beforeenteringdeeppowerdownthedrammustbein anallbanksidlestatewithnoactivityontheda tabus.upon enteringdeeppowerdownalldatawillbelost.whi leindeeppowerdownckemustbeheldinaconstan tlowstate. uponexitingdeeppowerdownnopcommandmustbema intainedfor200us.after200usacompleteinitiali zation routineisrequiredfollowingsteps4through11as definedinpowerupandinitializationsequences. mobile ddr sdram deep power-down entry and exit note: 1.clockmustbestablebeforeexitingdeeppowerd ownmode.thatis,theclockmustbecyclingwithin specificationsbyta0. 2.devicemustbeintheallbanksidlestateprior toenteringdeeppowerdownmode. 3.200usisrequiredbeforeanycommandcanbeappl ieduponexitingdpd. 4.dpd=deeppowerdowncommand. 5.uponexitingdeeppowerdownaprechargeallcom mandmustbeissuedfollowedbytwoautorefreshco mmandsandaload moderegistersequence. don't care nop dpd 4 nop valid 5 valid t 0 t 1 ta0 1 ta 1 tb 1 tck tih tis tch tcl tis tih tis tih tis trp 2 deep power down mode exit deep power down mode t=200us 3 ck ck cke com add dqs dq dm tis www..net
rev 1.2 / jun. 2008 58 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries cas latency definition caslatencydefinitionofmobileddrsdrammustbe mustbeloadedwhenallbanksareidle,andthecon trollermust waitthespecifiedtimebeforeinitiatingthesubse quentoperation. caslatencydefinition:withcl=3thefirstdata elementisvalidat(2*t ck +t ac )aftertheclockatwhichtheread commandwasregistered(seefigure2) cas latency definition note 1.dqtransitioningafterdqstransitionde finet dqsq window. 2.alldqmusttransitionbyt dqsq afterdqstransitions,regardlessoftac. 3.tacisthedqoutputwindowrelativeto ck,andisthelongtermcomponentofdqskew. read nop nop nop nop t 0 t 1 t 3 t 4 t 5 t 2 t 2n t 3n t 4n t 5n t 6 nop nop t 2 t 2n t 3 t 3n t 4 t 4n t 5 t 5n alldqvalues, collectively 2 cl = 3 tlz trpre tlz tdqsck tdqsck trpst dqs cmd ck ck tac tdqsq www..net
rev 1.2 / jun. 2008 59 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries clock stop mode clockstopmodeisafeaturesupportedbymobiledd rsdramdevices.itreducesclockrelatedpowercon sumption duringidleperiodsofthedevice. conditions:themobileddrsdramsupportsclocksto pincase: thelastaccesscommand(active,read,write,prec harge,autorefreshormoderegisterset)has executedtocompletion,includinganydataoutduri ngreadbursts;thenumberofrequiredclockpulses peraccess commanddependsonthedevice'sactimingparameter sandthe clockfrequency; therelatedtimingcondition(t rcd ,t wr ,t rp ,t rfc ,t mrd )hasbeenmet; ckeisheldhigh. whenallconditionshavebeenmet,thedeviceisei therin''idle''or''rowactive''state,andclock stopmodemaybe enteredwithckheldlowandck heldhigh.clockstopmodeisexitedwhenthecloc kisrestarted.nopscommand havetobeissuedforatleastoneclockcyclebefo rethenextaccesscommandmaybeapplied.addition alclockpulses mightberequireddependingonthesystemcharacter istics. figure1illustratestheclockstopmode: initiallythedeviceisinclockstopmode; theclockisrestartedwiththerisingedgeoft0 andanoponthecommandinputs; witht 1 avalidaccesscommandislatched;thiscommandis followedbynopcommandsinordertoallowforclo ck stopassoonasthisaccesscommandhascompleted; t n isthelastclockpulserequiredbytheaccesscom mandlatchedwitht 1. thetimingconditionofthisaccesscommandismet withthecompletionoft n ;thereforetnisthelastclockpulse requiredbythiscommandandtheclockisthenstop ped. clock stop mode ck add cmd nop nop nop nop valid clock stopped exitclock stopmode valid command enterclock stopmode don'tcare (highz) ck cmd t 0 t 1 t 2 t n cke dq, dqs timingcondition www..net
rev 1.2 / jun. 2008 60 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries data mask 1,2) mobileddrsdramusesadqwritemaskenablesignal (dm)whichmaskswritedata. datamaskingisonlyavailableinthewritecyclef ormobileddrsdram.datamaskingisavailableduri ngwrite,but datamaskingduringreadisnotavailable. dmcommandmasksburstwritedatawithreferenceto datastrobesignalanditisnotrelatedwithread data.dmcom mandcanbeinitiatedatboththerisingedgeandt hefallingedgeofthedqs.dmlatencyforwriteop erationiszero. forx32datai/o,mobileddrsdramisequippedwith dm0,dm1,dm2anddm3whichcontroldq0~dq7, dq8~dq15,dq16~dq23anddq24~dq31respectively. note: 1)mobilesdrsdramcanmaskbothreadandwriteda ta,butthereadmaskisnotsupportedbymobiledd rsdram. 2)differencesinfunctionsandspecifications(nex ttable) data masking (write cycle: bl=4) item mobile ddr sdram mobile sdr sdram datamask writemaskonly writemask/readmask write write dm cmd ck ck d0 d1 d3 d0 d1 d3 hi z dqs dq data masking data masking tdqss tdqsl tds tdh tdqsh hi z www..net
rev 1.2 / jun. 2008 61 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries power-up and initialization sequences mobileddrsdrammustbepoweredupandinitialized inapredefinedmanner.operationsproceduresothe rthank thosespecifiedmayresultinundefinedoperation. ifthereisanyinterruptiontothedevicepower,t heinitialization routineshouldbefollowed.thestepstobefollowe dfordeviceinitializationarelistedbelow. step1:providepower,thedevicecorepower(v dd )andthedevicei/opower(v ddq )mustbebroughtupsimulta neouslytopreventdevicelatchup.althoughnotre quired,itisrecommendedthatv dd andv ddq arefrom thesamepowersource.alsoassertandholdclocke nable(cke)toalvcmoslogichighlevel. step2:oncethesystemhasestablishedconsistent devicepowerandckeisdrivenhigh,itissafeto applystable clock. step3:theremustbeatleast200usofvalidclock sbeforeanycommandmaybegiventothedram.duri ngthis timenopordeselectcommandsmustbeissuedonthe commandbus. step4:issueaprechargeallcommand. step5:providenopsordeselectcommandsforatle astt rp time. step6:issueanautorefreshcommandfollowedbyn opsordeselectcommandforatleastt rfc time.issue thesecondautorefreshcommandfollowedbynopsor deselectcommandforatleastt rfc time. noteaspartoftheinitialization sequencetheremustbetwoautorefreshcommandsis sued.thetypical flowistoissuethematstep6,buttheymayalso beissuedbetweensteps10and11. step7:usingthemrscommand,loadthebasemoder egister.setthedesiredoperatingmodes. step8:providenopsordeselectcommandsforatle astt mrd time. step9:usingthemrscommand,programtheextended moderegisterforthedesiredoperatingmodes.not ethe orderofthebaseandextendedmoderegisterprogra mmingisnotimportant. step10:providenopordeselctcommandsforatlea stt mrd time. step11:thedramhasbeenproperlyinitializedand isreadyforanyvalidcommand. www..net
rev 1.2 / jun. 2008 62 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries theinitializationflowsequenceisbelow. initialization waveform sequence vdd vddq /clk clk cke cmd dm addr a10 ba0, ba1 dq, dqs t=200usec trp tmrd trfc tmrd vdd/vddq powered up clock stable auto refresh nop arf pre mrs arf act mrs code ra code code ra code ba0=l ba1=l ba ba0=l ba1=h trfc load mode register tch tcl tck all banks tis tih tis tih tis tih tis tih don't care high-z precharge all auto refresh load extended mode register www..net
rev 1.2 / jun. 2008 63 mobile ddr sdram 1gbit (32m x 32bit) H5MS1G22MFPseries/h5ms1g32mfpseries package information 90 ball 0.8mm pitch 8mm fbga [8.0 x 13.0 mm 2 , t=1.0mm max] unit[mm] 0.8 0.34 +/0.05 0.80typ. 1.00max 0.45 +/0.05 a1indexmark 1 3 . 0 t y p . bottom view 0.90 11.2typ. 6.40typ. 8.00typ. 0.8typ. 0.80 0.90. www..net

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